楊興華檢視原始碼討論檢視歷史
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楊興華，男，北京林業大學講師。
人物簡歷
2020.9-至今，北京林業大學理學院，講師
2017.7-2020.9，華為技術有限公司北京研究所，高級工程師
2011.9-2017.6，清華大學電子工程系，電子科學與技術，博士
2007.9-2011.6，北京郵電大學電子工程學院，電子信息科學與技術專業，學士
研究方向
1) 近似計算電路系統設計
2) 面向機器學習的高性能低功耗電路系統設計
主講課程
《傳感器電子學》、《人工智能基礎》、《高頻電子電路》、《FPGA實踐》
學術成果
論文
[1] Yang X, Xing Y, Qiao F, et al. Multistage Latency Adders Architecture Employing Approximate Computing[J]. Journal of Circuits, Systems and Computers, 2017, 26(03): 1750039. (SCI收錄, 檢索號: EE5SF，影響因子：0.308)
[2] Yang X, Huang N, Chen Y, et al. A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing[J]. IEICE Electronics Express, 2016, 13(23): 20160990.(SCI收錄, 檢索號: EG4KD，影響因子：0.344)
[3] Wu Y, Yang X, Plaza A, et al. Approximate Computing of Remotely Sensed Data: SVM Hyperspectral Image Classification as a Case Study[J]. IEEE Journal of Selected Topics in Applied Earth Observations & Remote Sensing, 2016, 9:1-13. (SCI收錄, 檢索號: EH0QN，影響因子：2.145)
[4] Yang X, Qiao F, Liu C, et al. Design of multi-stage latency adders using detection and sequence-dependence between successive calculations[C]//Circuits and Systems (ISCAS), 2014 IEEE International Symposium on. IEEE, 2014: 998-1001. (EI收錄,檢索號: 20143818165266)
[5] Yang X, Qiao F, Liu C, et al. Design of variable latency adder based on present and transitional states prediction[C]//Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on. IEEE, 2013: 120-125. (EI收錄, 檢索號: 20140517239230)
[6] Yang X, Xing Y, Qiao F, et al. Approximate Adder with Hybrid Prediction and Error Compensation Technique[C]//VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on. IEEE, 2016: 373-378. (EI收錄, 檢索號: 20164002870943)
[7] Liu C, Yang X, Qiao F, et al. Design methodology for approximate accumulator based on statistical error model[C]//Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific. IEEE, 2015: 237-242. (EI收錄, 檢索號: 20151500728205)
[8] Chen Y, Yang X, Qiao F, et al. A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis[C]//VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on. IEEE, 2016: 385-390. (EI收錄, 檢索號: 20164002870945)
專利
「一種可變延時預測方法及基於預測的可變延時加法器」，公開。[1]