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贾天宇，男，北京大学集成电路学院教授。毕业于美国西北大学，在哈佛大学完成博士后工作，加入北大前为卡耐基梅隆大学助理研究教授。
人物履历
教育及工作经历
2022至今，北京大学，助理教授
2021，美国卡耐基梅隆大学，助理研究教授
2020-2021，美国哈佛大学，博士后
2015-2019，美国西北大学，计算机工程，博士
2015-2018，美国西北大学，计算机工程，硕士
2011-2014，北京邮电大学，硕士
2007-2011，北京邮电大学，学士
研究方向
新型人工智能加速器芯片设计
异构系统集成SoC芯片设计与优化
可重构与可编程AI芯片架构研究
超低功耗数字电路设计
学术成果
论文
1.Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu, NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance, International Symposium on Microarchitecture (MICRO), Oct. 2020.
2.Tianyu Jia, Yuhao Ju, and Jie Gu, A compute-adaptive elastic clock chain technique with dynamic timing enhancement for 2D PE array based accelerators, International Solid-State Circuits Conference (ISSCC), Feb. 2020.
3.Tianyu Jia, Yijie Wei, Russ Joseph, and Jie Gu, An adaptive clock scheme exploiting instruction-based dynamic timing slack for a GPGPU architecture, IEEE Journal of Solid-State Circuits (JSSC), 2020.
4.Tianyu Jia, Yuhao Ju, and Jie Gu, A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique, IEEE Journal of Solid-State Circuits (JSSC), 2020.
5.Tianyu Jia, Russ Joseph, and Jie Gu, An adaptive clock management scheme exploiting instruction-based dynamic timing slack for general-purpose graphic processor unit with deep pipeline and out-of-order execution, International Solid-State Circuits Conference (ISSCC), Feb. 2019.[1]