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林信南，男，北京大学信息工程学院教授。
人物简历
1997年本科毕业于北京大学，并留校在微电子学研究所任助理工程师。1999年公派赴香港科技大学进修，2007年获香港科大微电子专业博士并返回北京大学深圳研究生院任讲师，2010年晋升副教授。
学术兼职
创建IEEE电子器件与集成电路深圳分会并曾任首任主席，是IEEE TED, EDL，Materials today等多个行业内著名期刊的审稿人。长期担任IEEE EDSSC(电子器件与集成电路会议)技术委员会委员，并担任IEEE EDSSC 2017技术委员会联合主席。
在半导体器件方向内，近几年所带课题组的具体研究内容为：
1. 用于EDA的新型仿真方法、工具及器件SPICE模型
a) 纳米集成电路前沿器件结构与模型：FinFET、TFET(隧穿场效应管)、无结器件；
b) 新型存储器件结构与模型：PCRAM(相变存储器)、RRAM（阻变存储）；
2. 电力电子器件
a) 宽禁带材料GaN(氮化镓)、SiC(碳化硅)器件物理、结构与工艺；
b) 硅基IGBT器件结构与工艺。
科研项目
1.国家重大科学研究计划(973A类)课题：移动介质与高速缓存中的PCRAM消费性电子产品开发；
2.国家自然科学基金面上项目：相变存储器件OTS与OMS物理机理和模型研究；
3.国家自然科学基金青年基金：纳米FinFET器件的退化模型和失效机理研究；
4.广东省自然科学基金面上项目：沟道垂直不均匀性、线粗糙和随机掺杂对无结FinFET器件性能影响与模型研究；
5.深圳基础研究杰出青年基金：新能源产业共性核心技术——高速大功率IGBT新型原胞结构与制造工艺研发。
学术成果
♦ Lining Zhang, Chenyue Ma, Xinnan Lin, Jin.He, Mansun Chan, “Chapter 11 Modeling FinFETs for CMOS Applications” in “Toward Quantum FinFET”, Published by Springer 2013；
♦ Xinnan Lin, Haijun Lou, Ying Xiao, Wenbo Wan, Lining Zhang, Mansun Chan, “Chapter: Silicon-Based Junctionless MOSFETs: Device Physics, Performance Boosters and Variations” in “Nanoscale Semiconductor Devices, MEMS, and Sensors: Outlook and Challenges”, published by Springer Publisher, New York, USA, in press.
最近5年代表性论文列表: 1) Hui Sun, Meihua Liu, Peng Liu, Xinnan Lin*, Xiaole Cui, Jianguo Chen, Dongmin Chen*，Performance optimization of lateral AlGaN/GaN HEMTs with cap gate on 150-mm silicon substrate, Solid-State Electronics，dx.doi.org/10.1016/j.sse.2017.01.006：28-32.
2) Wei Chen, Kaiwen Li, Yao Wang, Xiyuan Feng, Zhenwu Liao, Qicong Su, Xinnan Lin*, Zhubing He*, Black Phosphorus Quantum Dots for Hole Extraction of Typical Planar Hybrid Perovskite Solar Cells, J. Phys. Chem. Lett., DOI: 10.1021/acs.jpclett.6b02843, 591-598.
3） Ying Xiao, Xinnan Lin*, Haijun Lou*, Baili Zhang , Lining Zhang, Mansun Chan,”A Short Channel Double -Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect”, IEEE TRANSACTION ELECTRON DEVICES, 2016, 63(12)：4661-4667.
4) “Hongyu He, Yuan Liu, Binghui Yan, Xinnan Lin, Shengdong Zhang, “Analytical Drain Current Model for Organic Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.63,NO.11： 4423--4431.
5) Yunpeng Dong, Lining Zhang*, Xiangbin Li, Xinnan Lin*, Mansun Chan*, A Compact Model for Double-Gate Heterojunction Tunnel FETs, IEEE Transactions on Electron Devices, VOL.63,NO.11： 4506-4513.
6) Ying Xiao, Baili Zhang, Haijun Lou*, Lining Zhang, and Xinnan Lin*. A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs, IEEE Transactions on Electron Devices, 2016, 63(5):2176-2181.
7) Xinnan Lin*, Baili Zhang, Ying Xiao, Haijun Lou*, Lining Zhang*, and Mansun Chan. Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs, IEEE Transactions on Electron Devices, 2016, 63(3):959-965.
8) Chenyue Ma, Lining Zhang*, Xinnan Lin*, Mansun Chan, Universal framework for temperature dependence prediction of the negative bias temperature instability based in microscope pictures, Japanese Journal of Applied Physics, 55(4):044201 1-6,April 2016.
9) Dan Li, Baili ZhangA, Haijun Lou, Lining Zhang, Xinnan Lin, and Mansun Chan, Comparative Analysis of Carriers Statistics on MOSFET and Tunneling FET Characteristics, IEEE JEDS, vol 3,No 6, Nov. 2015, 447-451.
10) Haijun Lou, Baili Zhang, Dan Li, Xinnan Lin*, Jin He* and Mansun Chan, “Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers”, Semicond. Sci. Technol. 30 (2015) 015008 (7pp).
11) Jian Chen, Hang Meng, Frank X.C.Jiang, Xinnan Lin*, A Snapback-Free Shorted-Anode Insulated Gate Bipolar Transistor with an N-path Structure, Superlattices and Microstructures, 2015:201-209.
12) Yihan Chen, Kit Chu Kwong, Xinnan Lin*, Zhitang Song, and Mansun Chan*, 3-D Resistance Model for Phase-Change Memory Cell, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014/Vol 61, 4098-4104.
13) Haijun Lou, Dan Li, Yan Dong, Xinnan Lin*, JinHe*, Shengqi Yang and Mansun Chan, Suppression of tunneling leakage current in junctionless nanowire transistors, Semicond. Sci. Technol. 28 (2013) 125016 (6pp).
14) Haijun Lou, Dan Li, Yan Dong, Xinnan Lin*, Shengqi Yang, Jin He*, and Mansun Chan, Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors, Japanese Journal of Applied Physics 52 (2013) 104302.
15) Li Binghua, Frank X. C. Jiang, Li Zhigui, Lin Xinnan*, A trench accumulation layer controlled insulated gate bipolar transistor with a semi-SJ structure, Journal of Semiconductors, 2013/Vol.34/No.12.
16) Lining Zhang, Xinnan Lin*, Jin He*, and Mansun Chan*, "An Analytical Charge Model for Double-Gate Tunnel FETs", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012.
17) Wei Yiqun, Lin Xinnan*, Jia Yuchao, Cui Xiaole,Zhang Xing and Song Zhitang, Contact size scaling of a W-contact phase-change memory cell based on numerical simulation, Journal of Semiconductors, VOL.33, NO.11,November 2012, 114006- 1-5.
18) Wei Yiqun, Lin Xinnan*, Jia Yuchao, Cui Xiaole,He Jin, Zhang Xing, A SPICE model for a phase-change memory cell based on the analytical conductivity model, Journal of Semiconductors, VOL.33, NO.11,November 2012, 114004- 1-5.
19) Haijun Lou, Lining Zhang, Yunxi Zhu, Xinnan Lin*, Shengqi Yang, Jin He* and Mansun Chan, “A Junctionless Nanowire Transistor With Dual-Material-Gate”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 7, JULY 2012, PP 1829~1836.
20) Lin Li, Lining Zhang, Xinnan Lin*, Jin He, Chi On Chui and Mansun Chan*, Phase-Change Memory with Multi-Fin Thin-Film-Transistor Driver Technology,IEEE Electron Device Letters, VOL. 33, NO. 3, MARCH 2012,405-407.[1]